Field
This disclosure relates generally to data processing system architecture, and more specifically, to data processing systems having messaging.
Related Art
Multiprocessor computer systems have been known for many years, but their architecture, in particular how software running on one processor interacts with software running on another processor have generally made use of expensive and inefficient mechanisms such as shared memory and interprocessor interrupts. Thus facilities for cost-effective and efficient inter-program communication are rare. Further, shared-bus systems limited the maximum number of processors to a dozen or two (for cache-coherent SMPs), although ‘clusters’ could get much larger at the expense of having the expected cache behavior be managed explicitly by software instead of hardware.
Current VLSI technology is pushing system architectures to embrace an increasingly large number of processing units (or other intelligent agents) on a single chip. This means that increasingly software running on or controlling agents will need to efficiently communicate across processing units and agents. Current practice such as shared memory, interprocessor interrupts, etc., is slow and does not scale well, in addition to often requiring expensive and also difficult to scale cache-coherent shared memory.